The need for cooling microelectronic devices such as integrated circuit dice during operation is well recognized in the art. Typically, spot cooling of such devices as a result of non-uniform die power maps is needed in order to ensure reliable operation of the same, and in order to prevent device failure as a result of sustained elevated temperatures.
The cooling of microelectronic devices has been effected in various ways according to the prior art. Examples of current high volume manufacturing solutions for cooling microelectronic devices include cooling designs based upon liquid circulation or refrigeration. However, the latter solutions have proven to be costly. As an alternative, stand-alone thermoelectric coolers (hereinafter “TEC”'s) have been made available in order to offer a less costly and yet effective cooling option. As is well known, TEC's function based on the Peltier effect, according to which the passage of an electrical current through a junction including two dissimilar materials results in a cooling effect. When the current flow is reversed, a heating effect may be observed.
Current TEC's are generally fabricated according to three different regimes. According to a first regime, a single crystal ingot of TE material, such as a Bi or Te based alloy (for example, Bi2Te3 or BiSb), or such as PbTe or Si Ge, is provided. The ingot is then sliced into wafers, which are then diced into accurately sized blocks. Appropriate ones of the blocks are then P-doped (for example, with antimony) and N-doped (for example, with selenium) as desired to yield thermoelements. Thereafter, pairs of P- and N-doped thermoelements are plated with Ni, soldered in place along with undoped thermoelements, and sandwiched between metallized substrates to form a couple. The couple includes a pair of thermoelements consisting of one N-type and one P-type thermoelement connected electrically in series and thermally in parallel. The substrates may be made of alumina ceramic, although berylia ceramic and other materials may also be used. A number of couples may be joined together, such as via soldering, in order to form the TEC. For example, a single-stage module could be formed, which includes a single layer of thermoelectric couples. Thereafter, the TEC is mounted to a microelectronic device to cool the same. Mounting may be effected via compression with a thermal interface pad or thermal grease, solder or epoxy. The resulting assembly is a TEC mounted to a microelectronic device by way of a mounting material disposed therebetween, such as thermal grease, epoxy or solder.
According to a second regime, instead of working from an ingot as noted above, the thermoelements are fabricated by sputtering. In particular, three sputtering targets, typically made of TE material, are used to sputter the P-type, N-type, and undoped thermoelements. The thus formed thermoelements are then joined together electrically in series and thermally in parallel in order to form the TEC. The TEC may then be mounted to a microelectronic device as noted above.
According to a third regime, the thermoelements may have a superlattice structure. A superlattice structure is typically a structure consisting of alternating layers of two different semiconductor materials, each several nanometers thick. For example, a P- or N-type thermoelement may be made of alternating layers of P- or N-type semiconductor materials. Each of the layers is generally in the order of about 10 nm thick. A superlattice P-type thermoelement may include alternating layers of P-type bismuth chalcogenide materials, such as, for example, alternating layers of Bi2Te3/Sb2Te3 with layers of Bi0.5Sb1.5Te3. A superlattice N-type thermoelement may include alternating layers of P-type bismuth chalcogenide materials, such as, for example, alternating layers of Bi2Te3 with alternating layers of Bi2Se3. The respective superlattice structures may also be constructed from cobalt antimony skutteridite materials. Each of the layers of a superlattice thermoelement as noted above is joined to an adjacent layer via soldering, typically achieving a structure which is about 5 microns thick. The thus formed thermoelements are then joined together as noted above to form the TEC, which may then be mounted to a microelectronic device as noted above.
Disadvantageously, TEC's of the prior art are limited in their application for a number of reasons. Currently available TEC's do not necessarily accommodate heat removal requirements specific to a particular microelectronic device. In addition, such TEC's are limited in their heat flux capabilities by virtue of their thicknesses, which are typically in the range of millimeters. Moreover, the mounting materials necessary to mount currently available TEC's to the backside of microelectronic devices disadvantageously add to the thermal contact resistance of the overall package, thus compromising heat removal efficiency.